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1 lt1680 high power dc/dc step-up controller n high voltage: operation up to 60v max n high current: n-channel drive handles up to 10,000pf gate capacitance n programmable average current limiting n 5v reference output with 10ma external loading capability n fixed frequency current mode operation n oscillator synchronizable up to 200khz n undervoltage lockout with hysteresis n programmable start inhibit for power supply sequencing and protection n user adjustable slope compensation features descriptio n u the lt ? 1680 is a high power, current mode switching power supply controller optimized for boost topologies. the ic drives n-channel mosfet switches for dc/dc converters in applications up to 60v input. a high current gate drive output handles up to 10,000pf gate capaci- tance, enabling the construction of high power dc/dc converters. current sense common mode range up to 60v allows current sensing to be referenced to the input supply, eliminating the need for sense blanking circuits. the lt1680 incorporates programmable average current limiting allowing accurate limiting of dc current in the magnetics, independent of ripple current . user adjustable slope compensation provides stable operation at duty cycles up to 90%. the lt1680 operating frequency is programmable and can be synchronized up to 200khz. minimum off-time operation provides switch protection. the ic also incorpo- rates a soft start feature that is gated by both shutdown and undervoltage lockout conditions. applicatio n s u n high power single board systems n distributed power converters n industrial control systems n lead-acid battery back-up systems n automotive and heavy equipment , ltc and lt are registered trademarks of linear technology corporation. typical applicatio n u 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sl/adj c t i avg ss v c sgnd v fb v ref 5v ref sync 12v in gate pgnd run/shdn sense sense + + lt1680 mbr0520 r ct 15k r7 2k r vc 4.7k 1n914 c ct 1nf c3 2.2nf c vc 4.7nf c4 0.22 m f c2 1 m f c11 1nf 1680 ta01 c6 0.1 m f r6 75k r9 100k c12 1 m f m1 irfz44 3 d1 mbr20100ct 2 + c in 680 m f 25v 4 c out 680 m f 63v 3 v out 48v 5.2a l1 25 m h r sense 0.005 w 12v in 10v to 15v 24a (dc) + l1: kool m m , 18t #14 on 77314-a7 kool m m is a registered trademark of magnetics, inc. 12v to 48v, 250w boost output power (w) 0 efficiency (%) 90 95 100 200 1680 ta02 85 80 75 50 100 150 250 v out = 48v efficiency vs output power
2 lt1680 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u LT1680CN lt1680csw lt1680in lt1680isw order part number 1 2 3 4 5 6 7 8 top view sw package 16-lead plastic so wide n package 16-lead pdip 16 15 14 13 12 11 10 9 sl/adj c t i avg ss v c sgnd v fb v ref 5v ref sync 12v in gate pgnd run/shdn sense sense + t jmax = 125 c, q ja = 75 c/ w (n) t jmax = 125 c, q ja = 90 c/ w (sw) consult factory for military grade parts. (note 1) power supply voltage (12v in ) .................. C 0.3v to 20v sense amplifier input common mode ...... C 0.3v to 60v gate pin voltage ....................... C 0.3v to 12v in + 0.3v run/shdn pin voltage ......................... C 0.3v to 12v in all other pin voltages ................................. C 0.3v to 7v 5v reference output current ............................... 65ma operating ambient temperature range lt1680c .................................................. 0 c to 70 c lt1680i .............................................. C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c electrical characteristics 12v in = 12v, v vc = 2v, v fb = v ref = 1.25v, c gate = 3000pf, t a = 25 c unless otherwise noted. symbol parameter conditions min typ max units supply and protection i 12vin dc active supply current (note 2) gate output on l 15 22 ma gate output off 12 ma dc standby supply current v run < 0.5v l 65 110 m a v run/shdn shutdown rising threshold l 1.15 1.25 1.35 v v sshyst shutdown threshold hysteresis 15 mv i ss soft start charge current l 5814 m a v uvlo undervoltage lockout threshold - falling l 8.20 9.00 9.75 v undervoltage lockout threshold - rising l 9.35 9.95 v undervoltage lockout hysteresis l 200 350 mv 5v reference v ref5 5v reference voltage line, load and temperature l 4.75 5 5.25 v 5v reference line regulation 10v 12v in 15v l 3 5 mv/v i ref5 5v reference load range - dc l 10 ma pulse l 20 ma 5v reference load regulation 0 i ref5 20ma l C1.25 C 2 v/a i sc 5v reference short-circuit current 45 ma error amplifier v fb error amplifier reference voltage measured at feedback pin 1.242 1.250 1.258 v l 1.235 1.265 v i fb feedback input current v fb = v ref l 0.1 0.5 1.0 m a g m error amplifier transconductance l 1200 2000 3200 m mho a v error amplifier voltage gain l 1500 3000 v/v i vc error amplifier source current l 200 275 m a error amplifier sink current v fb C v ref = 500mv l 280 400 m a v vc absolute v c clamp voltage measured at v c pin 3.5 v
3 lt1680 electrical characteristics 12v in = 12v, v vc = 2v, v fb = v ref = 1.25v, c gate = 3000pf, t a = 25 c unless otherwise noted. note 2: supply current specification does not include external fet gate charge currents. actual supply currents will be higher and vary with operating frequency, operating voltages and the type of external fets used. see applications information. symbol parameter conditions min typ max units error amplifier v sense peak current limit threshold measured at sense inputs l 170 190 mv average current limit threshold measured at sense inputs, v cmsense = 10v l 110 120 130 mv v iavg average current limit threshold measured at i avg pin 2.5 v current sense amplifier a v amplifier dc gain measured at i avg pin 15 v/v v os amplifier input offset voltage 2v < v cmsense < 60v, l 0.1 mv sense + C sense C = 5mv i bias input bias current sink (v cmsense > 5v) l 45 75 m a source (v cmsense = 0v) l 700 1200 m a oscillator f o operating frequency, free run l 200 khz frequency programming error f o 200khz, r ct = 16.9k, c ct = 1000pf l C5 5 % i ct timing capacitor discharge current lt1680c l 2.20 2.5 2.75 ma lt1680i l 2.10 2.5 2.75 ma v sync sync input threshold rising edge l 0.8 2.0 v f sync sync frequency range f sync 200khz l f o 1.4f o output drivers v gate undervoltage output clamp 12v in 8.2v l 0.4 0.7 v standby mode output clamp v run < 0.5v l 0.1 v gate output on voltage l 11 11.9 12 v gate output off voltage l 0.4 0.7 v t gater gate output rise time l 60 200 ns t gatef gate output fall time l 60 140 ns the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.
4 lt1680 typical perfor m a n ce characteristics uw i 12vin supply current vs temperature gate transition time vs c gate 12v in supply voltage (v) 10 i 12vin supply current (ma ) 15 14 1680 g02 11 12 13 40 35 30 25 20 15 c g = 10nf c g = 4.7nf c g = 3.3nf c g = 1nf f o = 150khz t a = 25 c i 12vin supply current vs 12v in supply voltage 5v ref short-circuit current vs temperature temperature ( c) ?0 5v ref short-circuit current (ma) 60 55 50 45 40 35 30 25 75 1680 g04 ?5 0 50 100 125 5v ref = 0v i 12vin shutdown current vs temperature temperature ( c) ?0 i 12vin shutdown current ( a) 80 75 70 65 60 55 50 25 75 1680 g05 ?5 0 50 100 125 v ref voltage vs temperature temperature ( c) ?0 v ref voltage (v) 1.252 1.251 1.250 1.249 1.248 1.247 1.246 25 75 1680 g06 ?5 0 50 100 125 5v ref voltage vs temperature error amplifier voltage gain vs temperature error amplifier transconductance vs temperature temperature ( c) ?0 5v ref voltage (v) 5.01 5.00 4.99 4.98 25 75 1680 g07 ?5 0 50 100 125 temperature ( c) ?0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 25 75 1680 g08 ?5 0 50 100 125 error amplifier voltage gain (kv/v) temperature ( c) ?0 error amplifier transconductance (m ) 2.6 2.4 2.2 2.0 1.8 1.6 1.4 25 75 1680 g09 ?5 0 50 100 125 temperature ( c) ?0 i 12vin supply current (ma) 100 1680 g01 050 19 18 17 16 15 14 13 12 11 25 25 75 125 c gate (pf) 0 30 gate transition time (ns) 50 70 90 110 t f t r 130 150 t a = 25 c 2500 5000 7500 10000 1680 g03
5 lt1680 typical perfor m a n ce characteristics uw error amplifier source current vs temperature ss output current vs temperature average current limit threshold sense voltage vs common mode voltage temperature ( c) ?0 error amplifier source current ( a) 350 325 300 275 250 225 200 25 75 1680 g10 ?5 0 50 100 125 temperature ( c) ?0 ss output current ( a) 9 8 7 6 25 75 1680 g11 ?5 0 50 100 125 run/shdn rising threshold vs temperature temperature ( c) ?0 run/shdn rising threshold (v) 1.26 1.25 1.24 1.23 1.22 1.21 1.20 25 75 1680 g12 ?5 0 50 100 125 run/shdn threshold hysteresis vs temperature temperature ( c) ?0 run/shdn threshold hysteresis (mv) 14 13 12 11 10 9 8 25 75 1680 g13 ?5 0 50 100 125 v sense(cm) (v) 0 v sense (mv) 45 60 1680 g14 1 2 3 160 150 140 130 120 110 100 90 80 upper limit full operating temperature range typical lower limit uvlo thresholds vs temperature temperature ( c) ?0 v 12vin (v) 100 1680 g15 050 10.00 9.75 9.50 9.25 9.00 8.75 8.50 8.25 8.00 25 25 75 125 rising falling sense amplifier input bias current (source) vs temperature run/shdn input current vs pin voltage temperature ( c) ?0 i b(source) ( a) 100 1680 g16 050 1200 1100 1000 900 800 700 600 500 400 25 25 75 125 v cmsense = 0v sense amplifier input bias current (sink) vs temperature temperature ( c) ?0 i b(sink) ( a) 60 55 50 45 40 35 30 25 75 1680 g17 ?5 0 50 100 125 v cmsense = 10v run/shdn pin voltage (v) 0 run/shdn input current (na ) 2.0 1680 g18 0.5 1.0 1.5 (1.25) 800 700 600 500 400 300 200 100 0 .................................................................. typical upper limit full operating temperature range lower limit
6 lt1680 typical perfor m a n ce characteristics uw run/shdn input current vs pin voltage operating frequency (normalized) vs temperature maximum duty cycle vs r ct r ct (k ) 1246 maximum duty cycle (%) 100 90 80 70 60 50 40 30 20 10 0 10 20 40 60 100 1680 g20 i dischg = 2.1ma i dischg = 2.75ma full operating temperature range temperature ( c) ?0 operating frequency (normalized) 1.01 1.00 0.99 0.98 25 75 1680 g21 ?5 0 50 100 125 run/shdn pin voltage (v) 0 run/shdn input current ( a) 600 450 300 150 0 2468 1680 g19 10 12 upper limit lower limit typical full operating temperature range sl/adj (pin 1): slope compensation adjustment. allows increased slope compensation for certain high duty cycle applications. resistive loading of this pin increases effec- tive slope compensation. a resistor divider from the 5v ref pin can tailor the onset of additional slope compensation to specific regions in each switch cycle. pin can be floated or connected to 5v ref if no additional slope compensation is required. (see applications information section for slope compensation details.) c t (pin 2): oscillator timing pin. connect a capacitor (c ct ) to ground and a pull-up resistor (r ct ) to the 5v ref supply. typical values are c ct = 1000pf and 10k r ct 30k. i avg (pin 3): average current limit integration. fre- quency response characteristic is set using the 50k w output impedance and external capacitor to ground. averaging roll-off is typically set 1 to 2 orders of magni- tude below switching frequency. (typical capacitor value = 1000pf for f o = 100khz.) shorting this pin to sgnd will disable the average current limit function. in systems where open-loop inductor current occurs, such as boost supplies during output short-circuit condition and inrush periods, an external small-signal protection diode should be connected between i avg and the v c pin (anode to i avg pin, cathode to v c pin). see applications information. pi n fu n ctio n s uuu ss (pin 4): soft start. generates ramping threshold for regulator current limit during start-up and after uvlo events by sourcing about 10 m a into an external capacitor. v c (pin 5): error amplifier output. rc load creates domi- nant compensation in power supply regulation feedback loop to provide optimum transient response. (see appli- cations information section for compensation details.) sgnd (pin 6): small-signal ground. connect to negative terminal of c out . v fb (pin 7): error amplifier inverting input. used as voltage feedback input node for regulator loop. pin sources about 0.5 m a dc bias current to protect from an open feedback path condition. v ref (pin 8): bandgap generated voltage reference decoupling. connect a capacitor to signal ground. (typi- cal capacitor value ? 0.1 m f.) sense + (pin 9): current sense amplifier inverting input. connect to most positive (dc) terminal of current sense resistor. sense C (pin 10): current sense amplifier noninverting input. connect to most negative (dc) terminal of current sense resistor.
7 lt1680 run/shdn (pin 11): precision referenced shutdown. can be used as logic level input for shutdown control or as an analog monitor for input supply undervoltage protec- tion, etc. ic is enabled when run/shdn pin rising edge exceeds 1.25v. 15mv of hysteresis helps assure stable mode switching. all internal functions are disabled in shutdown mode. if this function is not desired, connect run/shdn to 12v in (typically through a 100k resistor). see applications information. pgnd (pin 12): power ground. references the output switch and internal driver control circuits. connect with low impedance trace to v in decoupling capacitor negative (ground) terminal. pi n fu n ctio n s uuu gate (pin 13): driver output. connect to gate of external power fet switch. 12v in (pin 14): 12v power supply input. bypass with at least 1 m f to pgnd. sync (pin 15): oscillator synchronization pin with ttl-level compatible input. input drives internal rising edge triggered one shot; sync signal on/off times should be 3 1 m s (10% to 90% duty cycle at 100khz). does not contain internal pull-up. connect to sgnd if not used. 5v ref (pin 16): 5v reference output. allows connection of external loads up to 10ma dc. reference is not available during shutdown. typically bypassed with at least 1 m f capacitor to sgnd. reference one shot 1.25v q uvlo circuit sr 5v ref 5v sync gate sense + sense i avg v in v out r sense 12v in pgnd sgnd osc c t r ct c ct v c sl/adj v ref v fb + + ic1 + 2.5v 1680 bd + ea 0.5 m a current sense amplifier ss 1.25v circuit enable run/shdn + run shdn 10 m a soft start 12v + 15 v out block diagra m w
8 lt1680 operatio n u basic control loop the lt1680 uses a constant frequency, current mode architecture. the timing of the ic is provided through an internal oscillator circuit that can be synchronized to an external clock and is programmable to operate at frequen- cies up to 200khz. the oscillator creates a modified sawtooth wave at its timing node (c t ) with a slow charge, rapid discharge characteristic. during typical boost converter operation, the mosfet switch is enabled at the start of each oscillator cycle. the switch stays enabled until the current through the switched inductor, sensed via the voltage across a series sense resistor (r sense ), is sufficient to trip the current com- parator (ic1) and reset the rs latch. when the switch is disabled, the inductor current is redirected to the supply output. if the current comparator threshold is not reached throughout the entire oscillator charge period, the rs latch is bypassed and the main switch is disabled during the oscillator discharge time. this minimum off time protects the switch, and is typically about 1 m s. the current comparator trip threshold is set on the v c pin, which is the output of a transconductance amplifier, or error amplifier (ea). the error amplifier integrates the difference between a feedback voltage (on the v fb pin) and an internal bandgap generated reference voltage of 1.25v, forming a signal that represents required load current. if the supplied current is insufficient for a given load, the output will droop, thus reducing the feedback voltage. the error amplifier responds by forcing current out of the v c pin, increasing the current comparator threshold. thus, the circuit will servo until the provided current is equal to the required load and the average output voltage is at the value programmed by the feedback resistors. input average current limit the output of the sense amplifier is monitored by a single pole integrator comprised of an external capacitor on the i avg pin and an output impedance of approximately 50k w . if this averaged value signal exceeds a level corresponding to 120mv across the external sense resistor, the current comparator threshold is clamped and cannot continue to rise in response to the error amplifier. thus, if average input current requirements exceed 120mv/r sense , the supply will current limit and the output voltage will fall out of regulation. the average current limit circuit monitors the sense amplifier output without slope compensation or ripple current contributions. therefore, the average input current limit threshold is unaffected by duty cycle. undervoltage lockout the lt1680 employs an undervoltage lockout circuit (uvlo) that monitors the 12v in supply rail. this circuit disables the output drive capability of the lt1680 if the 12v supply drops below 9v. unstable mode switching is prevented through 350mv of uvlo threshold hysteresis. shutdown the lt1680 can be put into low current shutdown by pulling the run/shdn pin low, disabling all circuit func- tions. the shutdown threshold is a bandgap referred voltage of 1.25v typical. use of a precision threshold on the shutdown circuit enables use of this pin for under- voltage protection of the v in supply and/or power supply sequencing. soft start the lt1680 incorporates a soft start function that oper- ates by slowly increasing current limit. this limit is controlled by internally clamping the v c pin to a low voltage that climbs with time as an external capacitor on the ss pin is charged with about 10 m a. this forces a graceful climb of output current source capability, and thus a graceful increase in output voltage until steady- state regulation is achieved. the soft start timing capaci- tor is clamped to ground during shutdown and during undervoltage lockout, yielding a graceful output recovery from either condition. 5v internal reference power for the oscillator timing elements and most other internal lt1680 circuits is derived from an internal 5v reference, accessible at the 5v ref pin. this supply pin can be loaded with up to 10ma dc (20ma pulsed) for convenient biasing of local elements such as control logic, etc.
9 lt1680 operatio n u slope compensation for duty cycles greater than 50%, slope compensation is required to prevent current mode duty cycle instability in the regulator control loop. the lt1680 employs internal slope compensation that is adequate for most applica- tions. however, if additional slope compensation is de- sired, it is available through the sl/adj pin. excessive slope compensation will cause reduction in maximum load current capability and is generally not desirable. applicatio n s i n for m atio n wu u u r sense selection for input current limit r sense generates a voltage that is proportional to the inductor current for use by the lt1680 current sense amplifier. the value of r sense is based on the required input current. the average current limit function has a typical threshold of 120mv/r sense , or: r sense = 120mv/i limit operation with v sense common mode voltage below 4.5v may slightly degrade current limit accuracy. see average current limit threshold tolerance vs common mode voltage in the typical performance characteristics sec- tion for more information. output voltage programming output voltage is programmed through a resistor feed- back network to the v fb pin (pin 7) on the lt1680. this pin is the inverting input of the error amplifier, which is internally referenced to 1.25v. the divider is ratioed to provide 1.25v at the v fb pin when the output is at its desired value. output voltage is thus set following the relation: v out = 1.25v(1 + r2/r1) when an external resistor divider is connected to the output as shown in figure 1. if high value feedback resistors are used, the input bias current of the v fb pin (1 m a maximum) could cause a slight increase in output voltage. a thevenin resistance at the v fb pin of < 5k is recommended. oscillator components r ct and c ct the lt1680 oscillator creates a modified sawtooth at its timing node (c t ) with a slow charge, rapid discharge characteristic. the discharge time (t disch ) corresponds to the minimum off time of the pwm controller. this limits maximum duty cycle (dc max ) to: dc max = 1 C (t disch )(f o ) this relation corresponds to the minimum value of the timing resistor (r ct ), which can be determined according to the following relation (r ct vs dc max graph appears in the typical performance characteristics section): r ct(min) ? [(0.8)(10 C3 )(1 C dc max )] C1 values for r ct > 15k yield maximum duty cycles above 90%. given a timing resistor value, the value of the timing capacitor (c ct ) can then be determined for desired oper- ating frequency (f o ) using the relation: c f r r ct o ct ct ? ()() ? ? ? () + () ? ? ? () 1 100 10 185 175 2 5 10 3 375 9 3 / /. . ../ a plot of operating frequency vs r ct and c ct is shown in figure 2. typical 100khz operational values are c ct = 1000pf and r ct = 16.9k. lt1680 v out v fb 6 7 r1 r2 1680 f01 sgnd figure 1. programming lt1680 output voltage
10 lt1680 applicatio n s i n for m atio n wu u u and a soft start timing capacitor c ss , the start-up delay time to full available average current will be: t ss = (1.8)(10 5 )(c ss ) shutdown functioninput undervoltage detect and threshold hysteresis the lt1680 run/shdn pin uses a bandgap generated reference threshold of about 1.25v. this precision thresh- old allows use of the run/shdn pin for both logic-level shutdown applications and analog monitoring applica- tions such as power supply sequencing. because an lt1680 controlled converter is a power trans- fer device, a voltage that is lower than expected on the input supply could require currents that exceed the sourc- ing capabilities of that supply, causing the system to lock- up in an undervoltage state. input supply start-up protection can be achieved by enabling the run/shdn pin using a resistor divider from the input supply to ground. setting the divider output to 1.25v when the supply is almost fully enabled prevents the lt1680 regulator from drawing large currents until the input supply is able to supply the required power. if additional hysteresis is desired for the enable function, an external feedback resistor can be used from the lt1680 regulator output. if connection to the regulator output is not desired, the 5v ref internal supply pin can be used. figure 3 shows an input supply sequencing configuration on a 24v input converter. this configuration yields an enable condition of 90% v in (~ 21.5v) with about 10% threshold hysteresis. the shutdown function can be disabled by connecting the run/shdn pin to the 12v in rail. this pin is internally clamped to 2.5v through a 20k series input resistance and will therefore draw 0.5ma when tied directly to 12v. this figure 3. input supply sequencing programming timing resistor (k w ) 3 7 11 15 19 23 27 31 35 39 43 47 oscillator frequency (khz) 200 180 160 140 120 100 80 60 40 1680 f02 c ct = 0.68nf c ct = 1nf c ct = 2.2nf c ct = 1.5nf figure 2. operating frequency vs r ct , c ct average current limit the average current limit function is implemented using an external capacitor (c avg ) connected from i avg to sgnd. this capacitor forms a single pole integrator with the 50k w output impedance of the i avg pin. the integrator corner frequency is typically set 1 to 2 orders of magnitude below the oscillator frequency and follows the relation: f C 3db = (3.2)(10 C6 )/c avg the average current limit function can be disabled by shorting the i avg pin directly to sgnd. in some applica- tions it is theoretically possible for the average current limit circuit to overdrive the error amplifier output (v c pin) beyond the operating range of the current sense compara- tor. these applications include those where open-loop system operation occurs, such as boost regulators in output short-circuit condition, or in systems with poor signal ground integrity. the potential for this overdrive can be eliminated by connecting an external clamp diode between the i avg and v c pins (anode to i avg and cathode to v c ). connection of this diode will have no adverse effects in any system and is recommended. this clamp is required for all boost converter topologies. soft start programming the lt1680 current control pin (v c ) limits inductor cur- rent to zero at voltages less than ? 0.7v through full average current limit at v c ? 2.5v, yielding 1.8v over the full regulation range of average load current. with the ss pin at 0v, the v c pin is clamped to its zero inductor current level. given the typical soft start charge current of 10 m a v in 24v 16 11 160k 390k 10k 1680 f03 5v ref run/shdn lt1680
11 lt1680 additional current can be minimized by making the con- nection through an external resistor (100k is typically used). when shutting down the lt1680, the run/shdn pin volt- age must remain between the shutdown threshold (~1.13v) and a minimum shutdown control limit voltage (see fig- ure 4) for a least 25 m s. if a digital input or fast moving clamp is used, this can be achieved by forcing a shutdown control voltage above the minimum limit or by using a simple integrator to increase the fall time of the input sig- nal. a single pole integrator stage must have a t 3 (7)(10 C5 ). applicatio n s i n for m atio n wu u u temperature ( c) 500 minimum shutdown control limit (mv) 600 700 800 40 20 0 20 1680 f04 40 60 80 figure 4. minimum shutdown control limit vs temperature figure 5 is an example of a digital control input clamp. a logic high signal pulls the run/shdn pin above its turn- on threshold through the diode. when a shutdown (logic low) signal is received, the run/shdn pin is forced to 0.95v via the resistor divider until shutdown is fully estab- lished and the 5v ref voltage collapses. r1 43k digital input r2 10k 1n914 1680 f05 5v ref lt1680 run/shdn figure 6 is an example of a digital control integration stage at the run/shdn input. the integrator has a t = (10)(10 3 ) ? (10)(10 C9 ) = (1.0)(10 C4 ). this circuit technique, however, delays initiation of controller shutdown about 125 m s from the reception of the shutdown signal (5v C 0v transition). figure 5. digital input shutdown level control r1 10k c1 10nf digital input 1680 f06 run/shdn lt1680 figure 6. digital input shutdown integration control figure 7 is an example of an integrator stage coupled with a 24v input power supply sequencing circuit similar to that shown in figure 3. the integrator stage allows use of an active shutdown clamp for implementation of both user- controlled shutdown and input power supply sequencing protection. inductor selection the inductor for an lt1680 converter is selected based on output power, operating frequency and efficiency require- 0.8v 1680 f08 2v 2.5v (vl) sync v ct (vh) free run synchronized figure 8. free run and synchronized oscillator waveforms (at c t pin) r1 160k r2 10k shdn r4 10k r3 390k v in 24v c1 10nf 1680 f07 lt1680 5v ref run/shdn figure 7. input supply sequencing with user-controlled shutdown oscillator synchronization the lt1680 oscillator generates a modified sawtooth waveform at the c t pin between low and high thresholds of 0.8v (vl) and 2.5v (vh) respectively. the oscillator can be synchronized by driving a ttl level pulse into the sync pin. this pin connects to a one shot circuit that reduces the oscillator high threshold to 2v for about 200ns. the sync input signal should have minimum on/off times of 3 1 m s.
12 lt1680 applicatio n s i n for m atio n wu u u ments. generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor ( d i). for a boost converter, the minimum inductor value for a given operating ripple current can be determined using the following relation: l vv v if v min in out in o out = () ()()( ) d given an inductor value (l), the peak inductor current is the sum of the average inductor current (i avg ) and half the inductor ripple current ( d i), or: ii vv v lf v pk avg in out in o out =+ () ()()( )( ) 2 the inductor core type is determined by peak current and efficiency requirements. the inductor core must with- stand this peak current without saturating, and the series winding resistance and core losses should be kept as small as is practical to maximize conversion efficiency. the lt1680 peak current threshold is 40% greater than the average limit threshold. slope compensation effects reduce this margin as duty cycle increases. this margin must be maintained to prevent peak current limit from corrupting the programmed value for average current limit. programming the peak ripple current to less than 15% of the desired average current limit value will assure proper operation of the average current limit feature through 90% duty cycle (see slope compensation). slope compensation current mode switching regulators that operate with a duty cycle greater than 50% and have continuous inductor current can exhibit duty cycle instability. while a regulator will not be damaged and may even continue to function acceptably during this type of subharmonic oscillation, an irritating high-pitched squeal is usually produced. the criterion for current mode duty cycle instability is met when the increasing slope of the inductor ripple current is less than the decreasing slope, which is the case at duty cycles greater than 50%. this condition is illustrated in figure 9a. the inductor ripple current starts at i 1 , the beginning of each oscillator switch cycle. current increases at a rate s1 until the current reaches the control trip level i 2 . the controller servo loop then disables the switch and inductor current begins to de- crease at a rate s2. if the current switch point (i 2 ) is perturbed slightly and increased by d i, the cycle time ends such that the minimum current point is increased by a factor of 1 + (s2/s1) to start the next cycle. on each successive cycle, this error is multiplied by a factor of s2/ s1. therefore, if s2/s1 is 3 1, the system is unstable. subharmonic oscillations can be eliminated by augment- ing the increasing ripple current slope (s1) in the control loop. this is accomplished by adding an artificial ramp on the inductor current waveform internal to the ic (with a slope s x ) as shown in figure 9b. if the sum of the slopes s1 + s x is greater than s2, this condition for subharmonic oscillation no longer exists. oscillator period time 0 0 ab ? i t1 i 2 i 1 s1 s1 s2 s2 s1 + s x 1680 f09 figure 9. inductor current at dc > 50% and slope compensation adjusted signal for boost topologies, the required additional current wave- form slope, or slope compensation, follows the relation: s sdc dc x 3 ()( ) () 12 1 1 for duty cycles less than 50% (dc < 0.5), s x is negative and is not required. for duty cycles greater than 50%, s x takes on values dependent on s1 and duty cycle. s1 is simply v in / l. this leads to a minimum inductance requirement for a given v in , duty cycle and slope compensation (s x ) of: l v s dc dc min in x = ? ? ? ? () 21 1 the lt1680 contains an internal slope compensation ramp that has an equivalent current referred value of:
13 lt1680 applicatio n s i n for m atio n wu u u this feature is implemented by referencing this pin via a resistor divider from the 5v ref pin to ground. the addi- tional slope compensation will be affected at the point in the oscillator waveform (at pin c t ) corresponding to the voltage set by the resistor divider. additional slope com- pensation can be calculated using the relation: s f rr x o th sense = ()() ()( ) 2500 amp/s where r th is the thevenin resistance of the resistor divider. actual compensation will actually be somewhat greater due to internal curvature correction circuitry that imposes an exponential increase in the slope compensa- tion waveform, further increasing the effective compensa- tion slope up to 20% for a given setting. design example: v in = 20v v out = 80v (dc = 0.75) r sense = 0.01 w f o = 100khz l = 20 m h the minimum inductor usable with no additional slope compensation is: l v h min 3 () w ()() ()()() =m 20 0 01 1 5 1 0 084 100000 1 0 75 47 6 .. .. . since l = 20 m h is less than l min , additional slope compensation is necessary. the total slope compensa- tion required is: s v h x 3 m ? ? ? ? () = 20 20 15 1 1075 210 6 . . ()( ) amp/s subtracting the internally generated slope compensation and solving for the required effective resistance at sl/adj yields: r f rf k eq o sense o ()() () ? ? ? ()()() = 2500 2 10 0 084 21 5 6 . . s = 0.084 f r x o sense ? ? ? ? amp/s where f o is oscillator frequency and r sense is the external current sense resistor. this yields a minimum inductance requirement of: l vr dc fdc min in sense o 3 ()( )( ) ()() - () [] 21 0 084 1 . a down side of slope compensation is that, since the ic servo loop senses an increase in perceived inductor cur- rent, the internal current limit functions are affected such that the maximum current capability of a regulator is reduced by the same amount as the effective current referred slope compensation. the lt1680, however, uses a current limit scheme that is independent of the slope compensation effects (average current limiting). this provides operation at any duty cycle with no reduction in current sourcing capability, provided ripple current peak amplitude is less than 15% of the current limit value. for example, if the converter is set up to average current limit at 10a, as long as the peak inductor current is less than 11.5a, duty cycles up to 90% can be achieved without compromising the average current limit value. if an inductor smaller than the minimum required for internal slope compensation (calculated above as l min ) is desired, additional slope compensation is necessary. the lt1680 provides this capability through the sl/adj pin. figure 10. maximum peak ripple current (normalized) vs duty cycle for average current limit duty cycle 0 1.10 maximum peak ripple current (i pk /i avg ) 1.15 1.25 1.30 1.35 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1680 f10 1.20 0.1 0.9 1.40 1.45
14 lt1680 applicatio n s i n for m atio n wu u u setting the resistor divider reference voltage to 2v assures that the additional compensation waveform will be en- abled at a 75% duty cycle. as shown in figure 11a, using r sl1 = 45k and r sl2 = 30k sets the desired reference voltage and has a r th of 18k, which meets both design requirements. figure 11b shows the slope compensation effective waveforms both with and without the sl/adj external resistors. in a typical lt1680 boost converter, the switch current is equal to the inductor current, but is chopped according to duty cycle (dc). the conduction loss (p loss ) for a given fet r ds(on) can be calculated using the relation: p loss ? (dc)(r ds(on) )(i avg 2 + [ d i 2 /12]) where i avg = average inductor current and d i = peak-to- peak inductor ripple current. the output diode is often a major source of power loss in switching regulators and selection of adequately rated diodes is important. in a boost converter, when the output voltage is significantly higher than the input voltage, the peak diode current becomes much higher than average output currents and diode current ratings must be ob- served with caution. the peak diode current is: i d(peak) = i avg + d i/2 and the average power dissipation (p d ) in the diode is: p d = (i out )(v f ) where v f is the forward voltage of the diode at peak current. the output diode must also be rated for maximum reverse voltages exceeding v out . c in and c out supply decoupling capacitor selection the large currents typical of lt1680 applications require special consideration for the regulator input and output supply decoupling capacitors. under normal steady state boost operation, output current provided by the converter is a square wave of duty cycle v in / v out , the average value being equal to the required dc load current (i out ). the continuity of the load current is main- tained by the output bypass capacitors. to prevent exces- sive output voltage ripple and undue capacitor heating (and associated catastrophic failure), low esr output capacitors sized for the maximum rms current must be used. this maximum capacitor rms current follows the relation: ii v v rms out out in ? ? ? ? ? / 1 12 capacitor ripple current ratings are often based on only 2000 hours (3 months) lifetime; it is advisable to derate either the esr or temperature rating of capacitors for increased mtbf. figure 11a. external slope compensation resistors 16 1 r sl1 45k r sl2 30k 1680 f11a 5v ref sl/adj lt1680 (0.084 + 0.139)(f o ) r sense (0.084)(f o ) r sense 2.5v 2v 0.8v dc = 0.75 1680 f11b figure 11b. slope compensation waveforms power mosfet and output rectifying diode selection lt1680 converter system parameters that dictate selec- tion criteria for the switch mosfet and output rectifying diode include maximum load current (i out ), inductor average current (i avg ) and inductor ripple current ( d i), and maximum input and output voltages. the switch mosfets selected must have a maximum operating v dss exceeding the maximum output voltage (v out ). v gs rated operating maximums must exceed the 12v in supply voltage. once voltage requirements have been determined, switch conduction resistance (r ds(on) ) can be determined based on allowable power dissipation.
15 lt1680 applicatio n s i n for m atio n wu u u the input bypass capacitors generally have less ripple current than the output bypass capacitors as the input current in a boost converter is continuous. input bypass capacitor selection can be made using ripple current ratings. peak-to-peak ripple current is equal to the induc- tor ripple current ( d i l ). efficiency considerations and heat dissipation high output power applications create an inherent con- cern regarding power dissipation in regulator compo- nents. although high efficiencies are achieved using the lt1680, the power dissipated in the regulator climbs to relatively high values when the load draws large amounts of power. even at 90% efficiency, a 500w application has conversion loss of 55w. i 2 r dissipation in the mosfet switch, sense resistor and inductor series resistance can generate substantial con- version loss under high current conditions. generally, the dominant i 2 r loss is evidenced in the fet switch, which is proportional to the steady-state duty cycle, or conduction time of the switch. for example, in a 5v to 48v boost converter, the duty cycle is: dc = 1 C (v in /v out ) dc = 1 C 5/48 ? 90% the fet switch conducts inductor current for almost 90% of the cycle time, and thus may require increased consid- eration for dissipating i 2 r power. gate drive buffer the lt1680 is designed to drive relatively large capacitive loads. however, in certain applications, efficiency im- provements can be realized by adding an external buffer stage to drive the gate of the fet switch. when the switch gate loads the driver output such that rise/fall times exceed 100ns, buffers can sometimes result in efficiency gains. buffers can also reduce effects of back injection into the gate driver output due to coupling of switch node transitions through the switch fet c miller . optimizing transient responseC compensation component values the dominant compensation point for an lt1680 con- verter is the v c pin (pin 5), or error amplifier output. this pin connects to an external series rc network, r vc and c vc . the infinite permutations of input/output filtering, capacitor esr, input voltage, load current, etc. make for an empirical method of optimizing loop response for a spe- cific set of conditions. loop response can be observed by injecting a step change in load current. this can be achieved by using a switchable load. with the load switching, the transient response of the output voltage can be observed with an oscilloscope. iterating through rc combinations will yield optimized response. refer to application note 19 in the 1990 linear applications handbook, volume 1 for more information. dimensions in inches (millimeters) unless otherwise noted. package descriptio n u n package 16-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. n16 1197 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () 0.255 0.015* (6.477 0.381) 0.770* (19.558) max 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm)
16 lt1680 typical applicatio n u C 48v to 5v 30w forward converter 220 m f 35v 5v ref c t i avg ss sync lt1680 sense + run/shdn 7 1 15 irf640 mbr0520lt1 mbr2045ct mbr2045ct 13 10 9 16 11 14 1 m f 0.1 m f 300pf 1.5nf t1 l1 20 m h 1nf 0.1 m f 0.1 m f l1: philips efd20-3f3-e63-s (core set, ai = 63nh/t 2 ) output 18t bifilar 22awg bias 54t bifilar 32awg t1: coiltronics vp5-1200, 1:1:1:1:1:1 (six windings each 77 m h) *sanyo cv-gx **sanyo os-con all resistors 1.4w, 1% unless indicated otherwise 0.22 m f 2.2nf 16k 20k 78.7k 20k 1m bav21 l1 7.5k 10 w 24k input com 48v input 24k 24k 4.75k 1k 1680 ta03 2n7000 2n3904 23 45 6128 12v in sense gate v c v fb sgnd pgnd sl/adj v ref + 1.5nf q7 2n5401 330 m f** 6.3v 5v 6a out output com 0.033 m f 33 w 4.22k 1.2k 33 w 0.015 w 1w 50 w 1w 1 m f 63v 1k + 220 m f* 35v + 220 m f* 35v + 220 m f* 35v + 220 m f* 35v + sw package 16-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) dimensions in inches (millimeters) unless otherwise noted. package descriptio n u part number description comments lt1268 7.5a, 150khz switching regulator integrated switch can be used in isolated flyback mode lt1270a 10a, 60khz switching regulator integrated switch can be used in isolated flyback mode lt1339 high power synchronous dc/dc controller operation to 60v, no shoot-through n-channel output drivers lt1370 500khz, 6a boost switching regulator integrated switch, regulates positive or negative outputs lt1371 500khz, 3a boost switching regulator integrated switch, regulates positive or negative outputs s16 (wide) 0396 note 1 0.398 ?0.413* (10.109 ?10.490) 16 15 14 13 12 11 10 9 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** 1680f lt/tp 0298 4k ? printed in usa ? linear technology corporation 1997 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com related parts

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